Full-day tutorial at the International Supercomputing Conference 2013 (ISC 13), June 16-20, 2013, Leipzig, Germany:

Node-Level Performance Engineering

Slides: isc13_tutorial_NLPE.pdf

Authors/Presenters

Georg Hager¹, Jan Treibig¹, and Gerhard Wellein²

¹ Erlangen Regional Computing Center
² Department of Computer Science
University of Erlangen-Nuremberg
Germany

{georg.hager,jan.treibig,gerhard.wellein}@fau.de

 

Abstract

This tutorial covers performance engineering approaches on the compute node level. “Performance Engineering” as we define it is more than employing tools to identify hotspots and bottlenecks. It is about developing a thorough understanding of the interactions between software and hardware. This process must start at the core, socket, and node level, where the code gets executed that does the actual computational work. Once the architectural requirements of a code are understood and correlated with performance measurements, the potential benefit of optimizations can often be predicted.
We start by giving an overview of modern processor and node architectures, including accelerators. Typical bottlenecks such as instruction throughput and data transfer are identified using kernel benchmarks and put into the architectural context. The impact of optimizations like SIMD vectorization, data layout transformations, and cache blocking is shown, and different aspects of a “holistic” node-level performance modeling and engineering strategy are demonstrated. Using the LIKWID multicore tool suite we show the importance of topology awareness, affinity enforcement, and hardware performance metrics. The latter are used to support the performance engineering process by supplying information that can validate or falsify performance models.