Two-part minisymposium at the SIAM Conference on Parallel Processing for Scientific Computing (SIAM PP18), Tokyo, Japan, March 7-10, 2018:
Performance Engineering from the Node Level to the Extreme Scale
Achieving hardware and energy efficiency is important for current large-scale numerical simulations and will be a key component in the exascale era. In a world of heterogeneous, highly parallel computer architectures with deep memory hierarchies, complex application scenarios, and a broad spectrum of algorithms, software developers can no longer rely on mystic “black-box” performance engineering computer programs. Instead, a thorough analysis and understanding of the complex interaction of software, data structures, algorithms, and hardware features, a.k.a. performance engineering, is required for implementing codes that allow for portable performance on the computer generations to come. The minisymposium addresses a broad range of topics in performance engineering for modern HPC architectures, ranging from recent advances in performance models and tools supporting a “white-box” performance engineering approach to application performance tuning cases studies. The presentations should point out the potentials and limitations of “white-box” performance engineering activities and demonstrate the wide spectrum of performance models used in the PE activities including simple performance expectations, automatic model parameter selections, and analytic models.
Georg Hager, Erlangen Regional Computing Center, Germany
Gerhard Wellein, Erlangen Regional Computing Center, Germany
Part 1 (MS29)
- Georg Hager, Erlangen Regional Computing Center, Germany: If It Doesn’t Work, We Learn Something: Instructive Case Studies in Performance Engineering.
- Martin Kronbichler, Technische Universität München, Germany: Fast Matrix-Free High-Order Discontinuous Galerkin Kernels: Performance Optimization and Modeling.
- Masatoshi Kawai, University of Tokyo, Japan: Efficient and Robust Parallel ILU Preconditioners for Quantum Eigenvalue Problems in ppOpen-HPC/ESSEX-II.
- Leonid Oliker, Lawrence Berkeley National Laboratory, USA: Roofline: a Throughput Oriented Performance Model.
Part 2 (MS41)
- Richard Vuduc, Georgia Institute of Technology, USA: Designing an Algorithm with a Tuning Knob that Controls its Power Consumption.
- Markus Püschel, ETH Zürich, Switzerland: Extending the Roofline Model: Bottleneck Analysis with Microarchitectural Constraints.
- Jeffrey S. Vetter, Oak Ridge National Laboratory, USA: Performance Engineering of Emerging Memory Systems.
- Felix Wolf, Technische Universitaet Darmstadt, Germany: Isoefficiency in Practice: Configuring and Understanding the Performance of Task-Based Applications.