Full-day tutorial at PPAM 2024, the 15th International Conference on Parallel Processing and Applied Mathematics, September 8-11, 2024, Ostrava, Czech Republic:
Core-Level Performance Engineering
Authors/Presenters
Jan Laukemann and Georg Hager
Erlangen National High Performance Computing Center (NHR@FAU)
FAU Erlangen-Nürnberg
Germany
{jan.laukemann,georg.hager}@fau.de
Slides and hands-on material: https://moodle.nhr.fau.de/course/view.php?id=114
Abstract
While many developers put a lot of effort into optimizing large-scale parallelism, they often neglect the importance of an efficient serial code. Even worse, slow serial code tends to scale very well, hiding the fact that resources are wasted because no definite hardware performance limit (“bottleneck”) is exhausted. This tutorial conveys the required knowledge to develop a thorough understanding of the interactions between software and hardware on the level of a single CPU core and the lowest memory hierarchy level (the L1 cache). We introduce general out-of-order core architectures and their typical performance bottlenecks using modern x86-64 (Intel Ice Lake) and ARM (Fujitsu A64FX) processors as examples. We then go into detail about x86 and AArch64 assembly code, specifically including vectorization (SIMD), pipeline utilization, critical paths, and loop-carried dependencies. We also demonstrate performance analysis and performance engineering using the Open-Source Architecture Code Analyzer (OSACA) in combination with a dedicated instance of the well-known Compiler Explorer. Various hands-on exercises will allow attendees to make their own experiments and measurements and identify in-core performance bottlenecks. Furthermore, we show real-life use cases to emphasize how profitable in-core performance engineering can be.